An HPC oriented workshop for sharing experiences and knowledge

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2017 Schedule

Thursday, 22 June 2017
(Room: Flint, 2nd Floor)

09:00-09:05 Organiser’s introduction
09:05-09:20 ARM-supported HPC tools

Presented by: Chris Goodyer
Abstract: The ARM HPC ecosystem is growing quickly. HPC centres around the world are moving from small-scale proof-of-concept boxes to much larger systems. One of the strengths of ARM is in having multiple partners involved. This means there are micro-architectures from different companies targeted at potentially different workloads. In such an environment, it is important that end-users have a consistent software story as they potentially test different systems. To ensure that high quality tools are being developed, ARM has a suite of software to help users get the best performance out of their chosen systems, both today and as they prepare for future ARM SVE architectures. In this presentation, we will explain these tools, including compilers and libraries and how the recent acquisition of Allinea has expanded our own offerings.

About the Speaker: Based at ARM's Manchester Design Centre, Chris leads the ARM Performance Libraries development team. They are responsible for optimizing the ARM vendor maths library, which provides BLAS, LAPACK and FFT functionality. He is also heavily involved in developing the ARM HPC software ecosystem. He holds a PhD from the University of Leeds on efficient adaptive methods for the numerical solution of PDEs and he subsequently worked at the university for twelve years on research on a variety of HPC and numerical modelling projects. Before joining ARM he was part of the HPC team at NAG working on supporting national HPC services such as HECToR, the UK's supercomputer, and the EU exascale project EXA2CT.
09:20-09:35 Allinea - ARM tools

Presented by: Olly Perks
Abstract: An introduction to the Allinea tools detailing their usage and capabilities. This will cover some of the new extensibility features, including custom metrics and JSON export. The talk will also cover the tool use within the ARM ecosystem, discussing the challenges of porting applications to the ARM ecosystem, and the use of Allinea tools to assist in validation and performance optimisation process.

About the Speaker: Oliver is a software engineer at ARM within the HPC tools group specialising in application profiling with the Allinea MAP tool, primarily working on European Horizon2020 projects. He obtained his PhD in analysing memory usage of HPC applications at scale, from the University of Warwick, and has since worked in industry, optimising large scale scientific codes, before joining ARM.
09:35-10:10 Barcelona Supercomputing Center (BSC) - Butterfly effects of porting scientific applications to ARM-based platforms

Presented by: Filippo Mantovani
Abstract: Since 2011 the EU Mont-Blanc project pushes the development of ARM-based compute platforms following the vision of leveraging the fast growing market of mobile technology for performing scientific computation. The process started almost 5 years ago with the development of prototypes based on Android dev-kits is now evolving beyond the research project, towards commercial computational platforms based not only on mobile SoCs, but also on server and HPC technology. In this talk we will introduce the experience gained porting system software, tools, and scientific applications to prototypes based on ARM technology within the Mont-Blanc project. By using several application examples, we will present behaviours observed on small prototypical platforms. We will describe how current limitations can represent fundamentals problems that programmers and architects will face developing and programming future HPC systems. Techniques to overcome these limitations will be also presented. The goal of the talk is to give a panoramic view of ARM based scientific computing from the Mont-Blanc perspective, supported by experience, lesson learned and test results.

About the Speaker: Filippo Mantovani is a postdoctoral research associate of the Mobile and embedded-based HPC group at the Barcelona Supercomputing Center (BSC). He graduated in mathematics and holds a PhD in Computer Science from University of Ferrara, Italy. He has been a scientific associate at the DESY laboratory in Zeuthen, Germany, and at the University of Regensburg, Germany. He spent most of his scientific career in computational physics, computer architecture and high-performance computing, contributing to the Janus, QPACE and QPACE2 projects. He joined BSC’s Mont-Blanc project in 2013, becoming in 2014 principal investigator of the project.
10:10-10:45 University of Michigan: Porting and Adapting Dense and Sparse Matrix Application to ARM’s SVE

Presented by: Jonathan Beaumont
Abstract: Recent trends in high-performance computing have resulted in the continued mapping of big-data applications with an increasingly wide range of data-access and control regularity to parallel architectures. This variety in workloads motivates the flexibility of target platforms. In this workshop we will discuss our efforts to port several applications to ARM’s SVE, including genomics workloads (which focus on dense vector computations) and graph analytic kernels (which focus on sparse matrix computations), and contrast the computational needs. We explore the advantages and shortcomings over other platforms and suggest future developments to microarchitectures employing these extensions.

About the Speaker: Jonathan Beaumont is a Ph.D. candidate in the Department of Computer Science and Engineering at the University of Michigan. His research involves the design of high-throughput microarchitectures and making them more accessible to programmers.
10:45-11:00 FLAGSHIP 2020 Project: Development of “Post-K” and ARM SVE

Presented by: Mitsuhisa Sato
Abstract: We are carrying out FLAGSHIP2020 project to develop and deploy the “post‐K” supercomputer as the successor of Japan's petascale facility, the K computer. ARM v8 with SVE ﴾Scalable Vector Extension﴿ is adopted as ISA of the manycore processor for “post‐K” system. In this talk, the overview of our projects will be described, and R&D for ARM SVE will be presented.

About the Speaker: Mitsuhisa Sato received the M.S. degree and the Ph.D. degree in information science from the University of Tokyo in 1984 and 1990. He was a senior researcher at Electrotechnical Laboratory from 1991 to 1996. From 2001, he was a professor of Graduate School of Systems and Information Engineering, University of Tsukuba. He has been working as a director of Center for computational sciences, University of Tsukuba from 2007 to 2013. Since October 2010, he is appointed to the research team leader of programming environment research team in Advanced Institute of Computational Science ﴾AICS﴿, RIKEN. He is a Professor Cooperative Graduate School Program and Professor Emeritus of University of Tsukuba.
11:00-11:30 Break
11:30-12:05 AVL – An ARM Porting Story - Optimizing a RBF Interpolation Solver for Energy on Heterogeneous Systems

Presented by: Patrick Schiffmann
Abstract: Coming Soon

About the Speaker: Patrick Schiffmann is a HPC software engineer at AVL, the world's largest independent company for development, simulation and testing technology of powertrains. He is working on a PhD in numerical simulations on energy-efficient heterogenous hardware. Previously he graduated from the University of Edinburgh with a degree and HPC and data science and worked as a quantitative analyst.
12:05-12:20 Cavium - ThunderX2 presentation

Presented by: Giri Chukkapalli
Abstract: Cavium has been leading the ARM server market with many firsts – including the first production deployment of dual socket ARMv8 silicon with ThunderX.  Cavium has also collaborated with leading software vendors to accelerate the HPC software ecosystem and is installed today in many of the elite HPC Labs and Research institutions worldwide.  Cavium will provide product and roadmap updates on ThunderX as well as additional ecosystem developments in HPC.

About the Speaker:Giri Chukkapalli is a Distinguished Engineer in the Data Center Group (DCG) of Cavium Inc. Giri is currently working on future Processor architectures for HPC and Data Center applications. Previously, Giri was a Technical Director in the PWI division of ING at Broadcom Corporation. . Prior to that, Giri was a Principal Engineer in the CTO Office of Cray Inc. where he explored future technologies in the HPC and Big Data space. Prior to working at Cray, he was CTO of Appro International, Inc. and worked on system architecture, dense packaging, efficient power delivery, and direct liquid cooling. Before that, he worked as a Principal Systems Architect in Systems Engineering division at SUN Microsystems responsible for winning and delivering several large-scale HPC systems. He has been working in the HPC industry for over 15 years.
12:20-12:55 Isambard - The World’s First Large-Scale Production 64-Bit ARM Supercomputer

Presented by: Simon McIntosh-Smith
Abstract: 2017 will see something of a minor revolution with the launch of a number of 64-bit ARM server chips that have been optimised for HPC workloads. These ARMv8 CPUs will for the first time offer performance comparable to mainstream x86 and POWER processors. In this talk we will describe Isambard, the world’s first large-scale production supercomputer based on these new ARMv8 processors. We will describe the architecture of the 10,000 core machine, explain Isambard’s mission, and disclose some early results from our software porting efforts.

About the Speaker: Simon McIntosh-Smith is a full Professor of High Performance Computing at the University of Bristol in the UK. He began his career as a microprocessor architect at Inmos and STMicroelectronics in the early 1990s, before co-designing the world's first fully programmable graphics processor (GPU) at Pixelfusion in 1999. In 2002 he co-founded ClearSpeed Technology where, as Director of Architecture and Applications, he co-developed the first modern many-core HPC accelerators. He now leads the High Performance Research Group at the University of Bristol, where his research focuses on performance portability and application based fault tolerance. He plays a key role in designing and procuring HPC services at the local, regional and national level, including the UK’s national HPC server, Archer. In 2016 he led the successful bid by the GW4 consortium along with the UK’s Met Office and Cray, to design and build ‘Isambard’, the world’s first large-scale production ARMv8-based supercomputer.
12:55-13:00 Closing remarks

Special thanks to:

About the Workshop

GoingARM will enable attendees to take in technical presentations by fellow applications programmers and tool authors who are currently using the ARM platform.

GoingARM is all about sharing experiences and knowledge. Attendees will gain from the first-hand knowledge of experienced scientific application programmers writing for the ARM platform, including topics such as: optimizing for 64-bit ARM, memory systems, scalability and vectorization.

Content specifically focuses on HPC applications and cross-over/emerging application areas such as machine learning, deep learning, bioinformatics, and analytics.


Jonathan Beard

Jonathan is a Staff Research Engineer focusing on scalable big data systems, in the Memory and Systems group at ARM Inc. Jonathan also serves as a technical advisor to start-ups, and has given talks ranging from C++ parallel runtimes to debating exascale memory architectures at SC. Jonathan Beard received a BS (Biology) and BA (International Studies) in 2005 from the Louisiana State University, MS (Bioinformatics) in 2010 from The Johns Hopkins University, and a PhD in Computer Science from Washington University in St. Louis in 2015. Jonathan served as a U.S. Army Officer from 2005 through July 2010 where he served in roles ranging from medical administrator, to Aide-de-Camp, to acting director of the medical informatics department for the U.S. Army in Europe. Jonathan's research interests also include online modeling of stream/data-flow parallel systems, streaming architectures, compute near data, and massively parallel processing. (direct contact: E-mail)

Roxana Rusitoru

Roxana Rusitoru is a Senior Research Engineer in ARM’s Research division, working in Software and Large Scale Systems. She joined ARM in 2012 after obtaining an MEng degree in Computing (Software Engineering) from Imperial College London in optimising unstructured mesh CFD applications on multicores via machine learning and code transformation. At ARM, amongst others, she has worked on Linux kernel optimizations aimed at HPC and sensitivity studies aimed to showcase ARM AArch64 microprocessor characteristics suitable for HPC. Most recently, she has been working on power-aware scheduling at OS level for heterogeneous cores and methodologies to identify representative sub-sections from multi-threaded applications. Some of her research interests are software performance optimization and next-gen heterogeneous architectures. Roxana has been a part of the Mont-Blanc 1 and 2 projects, and is now leading the Software ecosystem in Mont-Blanc 3, in addition to technical contributions. (direct contact: E-mail)

Workshop Contacts